Interdependency Study of Process and Design Parameter Scaling for Power Optimization of Nano-CMOS Circuits under Process Variation

In sub-65nm CMOS technology, switching power and gate as well as subthreshold leakage power are the major components of total power dissipation. To achieve power-performance tradeoffs one varies different process (Tox, K, Vth,) and design parameters (VDD, W). Techniques for (i) dual-K and dual-Tox have been proposed to reduce gate leakage, (ii) dual (multiple)-Vth has been introduced to minimize subthreshold leakage, and (iii) dual (multiple)-VDD has been used to optimize dynamic power. In view of the optimization regime above, the following question arises: If Tox, L, Vth, and VDD, etc. are scaled simultaneously, will one obtain a power and performance optimal circuit that has minimal gate leakage, minimal subthreshold leakage, and minimal dynamic power consumption? The objective of this paper is to essentially answer this question. Assuming dual values of Tox, Vth, and VDD for a particular K, we estimate the values for gate leakage, subthreshold leakage, dynamic power, and performance in architectural units such as adder, multiplexor, multiplier, etc. while accounting for process variation. Statistical variations in the parameters, each assumed to be Gaussian, are explicitly taken into account by using Monte Carlo simulations while characterizing the architectural units. The paper then analyzes the proportion of values of gate and subthreshold leakage and dynamic power in the total power consumption of these units. This in essence gives a relative and integrated perspective of various power-performance tradeoffs against the nominal case, thus serving as a guideline to help designers take appropriate decisions.